[PATCH v4 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe

[Kishon Vijay Abraham I]

x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.

Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
 .../boot/dts/ti/k3-j7200-common-proc-board.dts    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index def98f563336..4a7182abccf5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include <dt-bindings/mux/ti-serdes.h>
 #include <dt-bindings/phy/phy.h>
@@ -241,3 +242,17 @@
                resets = <&serdes_wiz0 3>;
        };
 };
+
+&pcie1_rc {
+       reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+};
+
+&pcie1_ep {
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+       status = "disabled";
+};
-- 
2.17.1