Re: [PATCH 1/2] cpufreq: sun50i: add a100 cpufreq support

[Clément Péron]

Hi Shuosheng,

On 04/12/2020 08:09, Shuosheng Huang wrote:

Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
let us use efuse_xlate to extract the differentiated part.

So you introduce 2 modifications here.
In this case it's better to have 2 patches.
One to introduce the efuse_xlate
And one to introduce the A100 support.

Regards,
Clement

Signed-off-by: Shuosheng Huang <huangshuosh...@allwinnertech.com>
---
  drivers/cpufreq/cpufreq-dt-platdev.c   |  1 +
  drivers/cpufreq/sun50i-cpufreq-nvmem.c | 81 ++++++++++++++++++++------
  2 files changed, 64 insertions(+), 18 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3776d960f405..2ebf5d9cb616 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = {
   */
  static const struct of_device_id blacklist[] __initconst = {
        { .compatible = "allwinner,sun50i-h6", },
+       { .compatible = "allwinner,sun50i-a100", },

{ .compatible = "calxeda,highbank", },

        { .compatible = "calxeda,ecx-2000", },
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c 
b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 9907a165135b..044e44a763f5 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -21,21 +21,63 @@

#define NVMEM_MASK 0x7

  #define NVMEM_SHIFT   5
+#define SUN50I_A100_NVMEM_MASK         0xf
+#define SUN50I_A100_NVMEM_SHIFT                12
+
+#define SUN50I_H6_NVMEM_MASK           0x7
+#define SUN50I_H6_NVMEM_SHIFT          5
+
+struct sunxi_cpufreq_soc_data {
+       u32 (*efuse_xlate)(void *efuse);
+};

static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev; +static u32 sun50i_a100_efuse_xlate(void *efuse)

+{
+       u32 efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &
+                         SUN50I_A100_NVMEM_MASK;
+
+       switch (efuse_value) {
+       case 0b100:
+               return 2;
+       case 0b010:
+               return 1;
+       default:
+               return 0;
+       }
+}
+
+static u32 sun50i_h6_efuse_xlate(void *efuse)
+{
+       u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
+                         SUN50I_H6_NVMEM_MASK;
+
+       /*
+        * We treat unexpected efuse values as if the SoC was from
+        * the slowest bin. Expected efuse values are 1-3, slowest
+        * to fastest.
+        */
+       if (efuse_value >= 1 && efuse_value <= 3)
+               return efuse_value - 1;
+       else
+               return 0;
+}
+
  /**
   * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
+ * @soc_data: pointer to sunxi_cpufreq_soc_data context
   * @versions: Set to the value parsed from efuse
   *
   * Returns 0 if success.
   */
-static int sun50i_cpufreq_get_efuse(u32 *versions)
+static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data 
*soc_data,
+                                   u32 *versions)
  {
        struct nvmem_cell *speedbin_nvmem;
        struct device_node *np;
        struct device *cpu_dev;
-       u32 *speedbin, efuse_value;
+       u32 *speedbin;
        size_t len;
        int ret;

@@ -68,17 +110,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)

        if (IS_ERR(speedbin))
                return PTR_ERR(speedbin);

- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;

-
-       /*
-        * We treat unexpected efuse values as if the SoC was from
-        * the slowest bin. Expected efuse values are 1-3, slowest
-        * to fastest.
-        */
-       if (efuse_value >= 1 && efuse_value <= 3)
-               *versions = efuse_value - 1;
-       else
-               *versions = 0;
+       *versions = soc_data->efuse_xlate(speedbin);

kfree(speedbin);

        return 0;
@@ -86,18 +118,23 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)

static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)

  {
+       const struct of_device_id *match;
        struct opp_table **opp_tables;
        char name[MAX_NAME_LEN];
        unsigned int cpu;
        u32 speed = 0;
        int ret;

+ match = dev_get_platdata(&pdev->dev);

+       if (!match)
+               return -EINVAL;
+
        opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables),
                             GFP_KERNEL);
        if (!opp_tables)
                return -ENOMEM;

- ret = sun50i_cpufreq_get_efuse(&speed);

+       ret = sun50i_cpufreq_get_efuse(match->data, &speed);
        if (ret)
                return ret;

@@ -163,8 +200,17 @@ static struct platform_driver sun50i_cpufreq_driver = {

        },
  };

+static const struct sunxi_cpufreq_soc_data sun50i_a100_data = {

+       .efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
+static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
+       .efuse_xlate = sun50i_h6_efuse_xlate,
+};
+
  static const struct of_device_id sun50i_cpufreq_match_list[] = {
-       { .compatible = "allwinner,sun50i-h6" },
+       { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
+       { .compatible = "allwinner,sun50i-a100", .data = &sun50i_a100_data >    
       {}
  };

@@ -198,9 +244,8 @@ static int __init sun50i_cpufreq_init(void)

        if (unlikely(ret < 0))
                return ret;

- sun50i_cpufreq_pdev =

-               platform_device_register_simple("sun50i-cpufreq-nvmem",
-                                               -1, NULL, 0);
+       sun50i_cpufreq_pdev = platform_device_register_data(NULL,
+               "sun50i-cpufreq-nvmem", -1, match, sizeof(*match));
        ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
        if (ret == 0)
                return 0;