This driver is intended to work with the multimedia block which
contains display and camera subsystems:
LCDIF
ISI
MIPI CSI
MIPI DSI
Signed-off-by: Adam Ford <aford...@gmail.com>
---
drivers/clk/imx/clk-blk-ctl-imx8mn.c | 80 ++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/clk/imx/clk-blk-ctl-imx8mn.c
b/drivers/clk/imx/clk-blk-ctl-imx8mn.c
new file mode 100644
index 000000000000..917514212270
--- /dev/null
+++ b/drivers/clk/imx/clk-blk-ctl-imx8mn.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Compass Eletronics Group, LLC
+ */
+
+#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/reset/imx8mn-reset.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "clk.h"
+#include "clk-blk-ctl.h"
+
+#define IMX_MEDIA_BLK_CTL_SFT_RSTN 0x0
+#define IMX_MEDIA_BLK_CTL_CLK_EN 0x4
+#define IMX_MEDIA_BLK_CTL_MIPI_RST 0x8
+
+static struct imx_blk_ctl_hw imx8mn_media_blk_ctl_hws[] = {
+ /* clocks */
+ IMX_BLK_CTL_CLK_GATE("mipi_dsi_pclk",
IMX8MN_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK, 0x4, 0, "dsi_core"),
+ IMX_BLK_CTL_CLK_GATE("mipi_dsi_clkref",
IMX8MN_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF, 0x4, 1, "dsi_phy_ref"),
+ IMX_BLK_CTL_CLK_GATE("mipi_csi_pclk",
IMX8MN_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK, 0x4, 2, "camera_pixel_clk"),
+ IMX_BLK_CTL_CLK_GATE("mipi_csi_aclk",
IMX8MN_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"),
+ IMX_BLK_CTL_CLK_GATE("lcdif_pixel_clk",
IMX8MN_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL, 0x4, 4, "disp_pixel"),
+ IMX_BLK_CTL_CLK_GATE("lcdif_apb_clk",
IMX8MN_CLK_MEDIA_BLK_CTL_LCDIF_APB, 0x4, 5, "disp_apb"),
+ IMX_BLK_CTL_CLK_GATE("isi_proc_clk", IMX8MN_CLK_MEDIA_BLK_CTL_ISI_PROC,
0x4, 6, "disp_axi_root_clk"),
+ IMX_BLK_CTL_CLK_GATE("isi_apb_clk", IMX8MN_CLK_MEDIA_BLK_CTL_ISI_APB,
0x4, 7, "disp_apb_root_clk"),
+ IMX_BLK_CTL_CLK_GATE("bus_blk_clk", IMX8MN_CLK_MEDIA_BLK_CTL_BUS_BLK,
0x4, 8, "disp_axi_root_clk"),
+
+ /* resets */
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK, 0, 0),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF, 0, 1),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK, 0, 2),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK, 0, 3),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL, 0, 4),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_LCDIF_APB, 0, 5),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_ISI_PROC, 0, 6),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_ISI_APB, 0, 7),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_BUS_BLK, 0, 8),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_S_RESET, 0x8, 16),
+ IMX_BLK_CTL_RESET(IMX8MN_MEDIA_BLK_CTL_RESET_MIPI_M_RESET, 0x8, 17),
+};
+
+const struct imx_blk_ctl_dev_data imx8mn_media_blk_ctl_dev_data __initconst = {
+ .hws = imx8mn_media_blk_ctl_hws,
+ .hws_num = ARRAY_SIZE(imx8mn_media_blk_ctl_hws),
+ .clocks_max = IMX8MN_CLK_MEDIA_BLK_CTL_END,
+ .resets_max = IMX8MN_MEDIA_BLK_CTL_RESET_NUM,
+ .pm_runtime_saved_regs_num = 3,
+ .pm_runtime_saved_regs = {
+ IMX_MEDIA_BLK_CTL_SFT_RSTN,
+ IMX_MEDIA_BLK_CTL_CLK_EN,
+ IMX_MEDIA_BLK_CTL_MIPI_RST,
+ },
+};
+
+static const struct of_device_id imx8mn_blk_ctl_of_match[] = {
+ {
+ .compatible = "fsl,imx8mn-media-blk-ctl",
+ .data = &imx8mn_media_blk_ctl_dev_data
+ },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8mn_blk_ctl_of_match);
+
+static struct platform_driver imx_blk_ctl_driver = {
+ .probe = imx_blk_ctl_probe,
+ .driver = {
+ .name = "imx8mn-blk-ctl",
+ .of_match_table = of_match_ptr(imx8mn_blk_ctl_of_match),
+ .pm = &imx_blk_ctl_pm_ops,
+ },
+};
+module_platform_driver(imx_blk_ctl_driver);
--
2.25.1
