Hi Mauro, I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20201023] [cannot apply to linuxtv-media/master sound/for-next pci/next mkp-scsi/for-next scsi/for-next linus/master v5.9 v5.9-rc8 v5.9-rc7 v5.9] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/Fix-several-bad-kernel-doc-markups/20201024-004025 base: 9695c4ff26459ff5bfe25c7d6179e4c9c00e1363 config: riscv-randconfig-r002-20201024 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 147b9497e79a98a8614b2b5eb4ba653b44f6b6f0) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/0day-ci/linux/commit/002bbfc5a97ce37daf3c570e0edd28fa0c7de5b8 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Mauro-Carvalho-Chehab/Fix-several-bad-kernel-doc-markups/20201024-004025 git checkout 002bbfc5a97ce37daf3c570e0edd28fa0c7de5b8 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> All warnings (new ones prefixed by >>): >> drivers/clk/analogbits/wrpll-cln28hpc.c:223: warning: expecting prototype >> for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead vim +223 drivers/clk/analogbits/wrpll-cln28hpc.c 7b9487a9a5c41ce Paul Walmsley 2019-04-30 199 7b9487a9a5c41ce Paul Walmsley 2019-04-30 200 /** 7b9487a9a5c41ce Paul Walmsley 2019-04-30 201 * wrpll_configure() - compute PLL configuration for a target rate 7b9487a9a5c41ce Paul Walmsley 2019-04-30 202 * @c: ptr to a struct wrpll_cfg record to write into 7b9487a9a5c41ce Paul Walmsley 2019-04-30 203 * @target_rate: target PLL output clock rate (post-Q-divider) 7b9487a9a5c41ce Paul Walmsley 2019-04-30 204 * @parent_rate: PLL input refclk rate (pre-R-divider) 7b9487a9a5c41ce Paul Walmsley 2019-04-30 205 * 7b9487a9a5c41ce Paul Walmsley 2019-04-30 206 * Compute the appropriate PLL signal configuration values and store 7b9487a9a5c41ce Paul Walmsley 2019-04-30 207 * in PLL context @c. PLL reprogramming is not glitchless, so the 7b9487a9a5c41ce Paul Walmsley 2019-04-30 208 * caller should switch any downstream logic to a different clock 7b9487a9a5c41ce Paul Walmsley 2019-04-30 209 * source or clock-gate it before presenting these values to the PLL 7b9487a9a5c41ce Paul Walmsley 2019-04-30 210 * configuration signals. 7b9487a9a5c41ce Paul Walmsley 2019-04-30 211 * 7b9487a9a5c41ce Paul Walmsley 2019-04-30 212 * The caller must pass this function a pre-initialized struct 7b9487a9a5c41ce Paul Walmsley 2019-04-30 213 * wrpll_cfg record: either initialized to zero (with the 7b9487a9a5c41ce Paul Walmsley 2019-04-30 214 * exception of the .name and .flags fields) or read from the PLL. 7b9487a9a5c41ce Paul Walmsley 2019-04-30 215 * 7b9487a9a5c41ce Paul Walmsley 2019-04-30 216 * Context: Any context. Caller must protect the memory pointed to by @c 7b9487a9a5c41ce Paul Walmsley 2019-04-30 217 * from simultaneous access or modification. 7b9487a9a5c41ce Paul Walmsley 2019-04-30 218 * 7b9487a9a5c41ce Paul Walmsley 2019-04-30 219 * Return: 0 upon success; anything else upon failure. 7b9487a9a5c41ce Paul Walmsley 2019-04-30 220 */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 221 int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, 7b9487a9a5c41ce Paul Walmsley 2019-04-30 222 unsigned long parent_rate) 7b9487a9a5c41ce Paul Walmsley 2019-04-30 @223 { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 224 unsigned long ratio; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 225 u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 226 u32 best_f, f, post_divr_freq; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 227 u8 fbdiv, divq, best_r, r; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 228 int range; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 229 7b9487a9a5c41ce Paul Walmsley 2019-04-30 230 if (c->flags == 0) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 231 WARN(1, "%s called with uninitialized PLL config", __func__); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 232 return -EINVAL; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 233 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 234 7b9487a9a5c41ce Paul Walmsley 2019-04-30 235 /* Initialize rounding data if it hasn't been initialized already */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 236 if (parent_rate != c->parent_rate) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 237 if (__wrpll_update_parent_rate(c, parent_rate)) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 238 pr_err("%s: PLL input rate is out of range\n", 7b9487a9a5c41ce Paul Walmsley 2019-04-30 239 __func__); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 240 return -ERANGE; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 241 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 242 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 243 7b9487a9a5c41ce Paul Walmsley 2019-04-30 244 c->flags &= ~WRPLL_FLAGS_RESET_MASK; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 245 7b9487a9a5c41ce Paul Walmsley 2019-04-30 246 /* Put the PLL into bypass if the user requests the parent clock rate */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 247 if (target_rate == parent_rate) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 248 c->flags |= WRPLL_FLAGS_BYPASS_MASK; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 249 return 0; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 250 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 251 7b9487a9a5c41ce Paul Walmsley 2019-04-30 252 c->flags &= ~WRPLL_FLAGS_BYPASS_MASK; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 253 7b9487a9a5c41ce Paul Walmsley 2019-04-30 254 /* Calculate the Q shift and target VCO rate */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 255 divq = __wrpll_calc_divq(target_rate, &target_vco_rate); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 256 if (!divq) 7b9487a9a5c41ce Paul Walmsley 2019-04-30 257 return -1; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 258 c->divq = divq; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 259 7b9487a9a5c41ce Paul Walmsley 2019-04-30 260 /* Precalculate the pre-Q divider target ratio */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 261 ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 262 7b9487a9a5c41ce Paul Walmsley 2019-04-30 263 fbdiv = __wrpll_calc_fbdiv(c); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 264 best_r = 0; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 265 best_f = 0; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 266 best_delta = MAX_VCO_FREQ; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 267 7b9487a9a5c41ce Paul Walmsley 2019-04-30 268 /* 7b9487a9a5c41ce Paul Walmsley 2019-04-30 269 * Consider all values for R which land within 7b9487a9a5c41ce Paul Walmsley 2019-04-30 270 * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R 7b9487a9a5c41ce Paul Walmsley 2019-04-30 271 */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 272 for (r = c->init_r; r <= c->max_r; ++r) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 273 f_pre_div = ratio * r; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 274 f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 275 f >>= (fbdiv - 1); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 276 7b9487a9a5c41ce Paul Walmsley 2019-04-30 277 post_divr_freq = div_u64(parent_rate, r); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 278 vco_pre = fbdiv * post_divr_freq; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 279 vco = vco_pre * f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 280 7b9487a9a5c41ce Paul Walmsley 2019-04-30 281 /* Ensure rounding didn't take us out of range */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 282 if (vco > target_vco_rate) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 283 --f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 284 vco = vco_pre * f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 285 } else if (vco < MIN_VCO_FREQ) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 286 ++f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 287 vco = vco_pre * f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 288 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 289 7b9487a9a5c41ce Paul Walmsley 2019-04-30 290 delta = abs(target_rate - vco); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 291 if (delta < best_delta) { 7b9487a9a5c41ce Paul Walmsley 2019-04-30 292 best_delta = delta; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 293 best_r = r; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 294 best_f = f; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 295 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 296 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 297 7b9487a9a5c41ce Paul Walmsley 2019-04-30 298 c->divr = best_r - 1; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 299 c->divf = best_f - 1; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 300 7b9487a9a5c41ce Paul Walmsley 2019-04-30 301 post_divr_freq = div_u64(parent_rate, best_r); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 302 7b9487a9a5c41ce Paul Walmsley 2019-04-30 303 /* Pick the best PLL jitter filter */ 7b9487a9a5c41ce Paul Walmsley 2019-04-30 304 range = __wrpll_calc_filter_range(post_divr_freq); 7b9487a9a5c41ce Paul Walmsley 2019-04-30 305 if (range < 0) 7b9487a9a5c41ce Paul Walmsley 2019-04-30 306 return range; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 307 c->range = range; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 308 7b9487a9a5c41ce Paul Walmsley 2019-04-30 309 return 0; 7b9487a9a5c41ce Paul Walmsley 2019-04-30 310 } 7b9487a9a5c41ce Paul Walmsley 2019-04-30 311 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
