Since kernel no longer writes to the vector, try to replace the vector mem type with read-only type and remove L_PTE_MT_VECTORS.
from Catalin in [1]: " > I don't think this matters since the kernel no longer writes to the > vectors page at run-time but it needs cleaning up a bit (and testing in > case I missed something). IOW, do we still need a dedicated mapping type > for the vectors or we can simply use the read-only user page attributes? " [1] https://lore.kernel.org/patchwork/patch/986574/ Cc: Russell King <li...@armlinux.org.uk> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Minchan Kim <minc...@kernel.org> Cc: Suren Baghdasaryan <sur...@google.com> Signed-off-by: Miles Chen <miles.c...@mediatek.com> --- arch/arm/include/asm/pgtable-2level.h | 1 - arch/arm/mm/mmu.c | 7 +++---- arch/arm/mm/proc-macros.S | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 385e7a32394e..438359d3675f 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -163,7 +163,6 @@ #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ #if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ab69250a86bc..0b6b377e2cce 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -536,12 +536,11 @@ static void __init build_mem_type_table(void) #ifndef CONFIG_ARM_LPAE /* - * We don't use domains on ARMv6 (since this causes problems with - * v6/v7 kernels), so we must use a separate memory type for user - * r/o, kernel r/w to map the vectors page. + * We no longer write to the vector pages ar run-time, to + * use read-only user page attribute for vector. */ if (cpu_arch == CPU_ARCH_ARMv6) - vecs_pgprot |= L_PTE_MT_VECTORS; + vecs_pgprot |= L_PTE_RDONLY; /* * Check is it with support for the PXN bit diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index dde1d6374250..f3e6551b4a7e 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -137,7 +137,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .long 0x00 @ unused .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused -- 2.18.0
