Hi Boris, On Wed 30.Sep'20 at 10:09:59 +0200, Borislav Petkov wrote:
On Tue, Sep 22, 2020 at 07:42:57PM +0800, shuo.a....@intel.com wrote:+static u32 acrn_cpuid_base(void) +{ + static u32 acrn_cpuid_base; + + if (!acrn_cpuid_base && boot_cpu_has(X86_FEATURE_HYPERVISOR)) + acrn_cpuid_base = hypervisor_cpuid_base("ACRNACRNACRN", 0); + + return acrn_cpuid_base; +} + +bool acrn_is_privileged_vm(void) +{ + return cpuid_eax(acrn_cpuid_base() | ACRN_CPUID_FEATURES) &What's that dance and acrn_cpuid_base static thing needed for? Why not simply: cpuid_eax(ACRN_CPUID_FEATURES) & ... ?
hypervisor_cpuid_base() searches reserved hypervisor cpuid region and return the base matched the right signature, the base might vary. So i put it here.
+ ACRN_FEATURE_PRIVILEGED_VM; +} +EXPORT_SYMBOL_GPL(acrn_is_privileged_vm);Also, if you're going to need more of those bit checkers acrn_is_<something> which look at ACRN_CPUID_FEATURES, just stash CPUID_0x40000001_EAX locally and use a acrn_has(ACRN_FEATURE_PRIVILEGED_VM) which does the bit testing.
Thanks. Currently, there is only one feature bit. I will introduce that you suggested with more feature bits to be tested. Thanks shuo
