The PMIC's interrupt is level low and should be pulled up.  The PMIC's
device node had pinctrl-0 property but it lacked pinctrl-names which
is required to apply the pin configuration.  The actual problem in DTS
was pointed out by Felix Radensky from Variscite.

Reported-by: Felix Radensky <feli...@variscite.com>
Fixes: 5f67317bd967 ("arm64: dts: imx8mm: correct interrupt flags")
Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index 4107fe914d08..49082529764f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -135,13 +135,10 @@
        pmic@4b {
                compatible = "rohm,bd71847";
                reg = <0x4b>;
+               pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_pmic>;
                interrupt-parent = <&gpio2>;
-               /*
-                * The interrupt is not correct. It should be level low,
-                * however with internal pull up this causes IRQ storm.
-                */
-               interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+               interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
                rohm,reset-snvs-powered;
 
                #clock-cells = <0>;
@@ -398,7 +395,7 @@
 
        pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x41
+                       MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x141
                >;
        };
 
-- 
2.17.1

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