The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 789521fca70ec8cb98f7257b880405e46f8a47a1 Gitweb: https://git.kernel.org/tip/789521fca70ec8cb98f7257b880405e46f8a47a1 Author: Krish Sadhukhan <krish.sadhuk...@oracle.com> AuthorDate: Thu, 17 Sep 2020 21:20:37 Committer: Borislav Petkov <b...@suse.de> CommitterDate: Fri, 18 Sep 2020 09:48:22 +02:00
x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains In some hardware implementations, coherency between the encrypted and unencrypted mappings of the same physical page is enforced. In such a system, it is not required for software to flush the page from all CPU caches in the system prior to changing the value of the C-bit for the page. So check that bit before flushing the cache. [ bp: Massage commit message. ] Suggested-by: Tom Lendacky <thomas.lenda...@amd.com> Signed-off-by: Krish Sadhukhan <krish.sadhuk...@oracle.com> Signed-off-by: Borislav Petkov <b...@suse.de> Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhuk...@oracle.com --- arch/x86/mm/pat/set_memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index d1b2a88..40baa90 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) /* * Before changing the encryption attribute, we need to flush caches. */ - cpa_flush(&cpa, 1); + cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); ret = __change_page_attr_set_clr(&cpa, 1);
