On 9/11/20 1:10 PM, Krish Sadhukhan wrote: ... >>> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD >>> hardware-enforced cache coherency */ >> That's an awfully generic name. We generally have "hardware-enforced >> cache coherency" already everywhere. :) >> >> This probably needs to say something about encryption, or even SEV >> specifically. > > How about X86_FEATURE_ENC_CACHE_COHERENCY ?
I think X86_FEATURE_SME_COHERENT would be the most appropriate name. That bit, as defined, looks totally specific to SME.
