[PATCH 5.8 013/186] habanalabs: set clock gating according to mask

[Greg Kroah-Hartman]

From: Ofir Bitton <obit...@habana.ai>

[ Upstream commit f44d23b9095abd91dad9f5f3add2a3149833ec83 ]

Once clock gating is set we enable clock gating according to mask,
we should also disable clock gating according to relevant bits.

Signed-off-by: Ofir Bitton <obit...@habana.ai>
Reviewed-by: Oded Gabbay <oded.gab...@gmail.com>
Signed-off-by: Oded Gabbay <oded.gab...@gmail.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 drivers/misc/habanalabs/gaudi/gaudi.c | 44 +++++++++++++--------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c 
b/drivers/misc/habanalabs/gaudi/gaudi.c
index 0261f60df5633..8b6cf722ddf8e 100644
--- a/drivers/misc/habanalabs/gaudi/gaudi.c
+++ b/drivers/misc/habanalabs/gaudi/gaudi.c
@@ -2564,6 +2564,7 @@ static void gaudi_set_clock_gating(struct hl_device *hdev)
 {
        struct gaudi_device *gaudi = hdev->asic_specific;
        u32 qman_offset;
+       bool enable;
        int i;
 
        /* In case we are during debug session, don't enable the clock gate
@@ -2573,46 +2574,43 @@ static void gaudi_set_clock_gating(struct hl_device 
*hdev)
                return;
 
        for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {
-               if (!(hdev->clock_gating_mask &
-                                       (BIT_ULL(gaudi_dma_assignment[i]))))
-                       continue;
+               enable = !!(hdev->clock_gating_mask &
+                               (BIT_ULL(gaudi_dma_assignment[i])));
 
                qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;
-               WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN);
+               WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
+                               enable ? QMAN_CGM1_PWR_GATE_EN : 0);
                WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
-                               QMAN_UPPER_CP_CGM_PWR_GATE_EN);
+                               enable ? QMAN_UPPER_CP_CGM_PWR_GATE_EN : 0);
        }
 
        for (i = GAUDI_HBM_DMA_1 ; i < GAUDI_DMA_MAX ; i++) {
-               if (!(hdev->clock_gating_mask &
-                                       (BIT_ULL(gaudi_dma_assignment[i]))))
-                       continue;
+               enable = !!(hdev->clock_gating_mask &
+                               (BIT_ULL(gaudi_dma_assignment[i])));
 
                qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;
-               WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN);
+               WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
+                               enable ? QMAN_CGM1_PWR_GATE_EN : 0);
                WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
-                               QMAN_COMMON_CP_CGM_PWR_GATE_EN);
+                               enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
        }
 
-       if (hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_0))) {
-               WREG32(mmMME0_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN);
-               WREG32(mmMME0_QM_CGM_CFG, QMAN_COMMON_CP_CGM_PWR_GATE_EN);
-       }
+       enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_0)));
+       WREG32(mmMME0_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
+       WREG32(mmMME0_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
 
-       if (hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_2))) {
-               WREG32(mmMME2_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN);
-               WREG32(mmMME2_QM_CGM_CFG, QMAN_COMMON_CP_CGM_PWR_GATE_EN);
-       }
+       enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_2)));
+       WREG32(mmMME2_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
+       WREG32(mmMME2_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
 
        for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
-               if (!(hdev->clock_gating_mask &
-                                       (BIT_ULL(GAUDI_ENGINE_ID_TPC_0 + i))))
-                       continue;
+               enable = !!(hdev->clock_gating_mask &
+                               (BIT_ULL(GAUDI_ENGINE_ID_TPC_0 + i)));
 
                WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset,
-                               QMAN_CGM1_PWR_GATE_EN);
+                               enable ? QMAN_CGM1_PWR_GATE_EN : 0);
                WREG32(mmTPC0_QM_CGM_CFG + qman_offset,
-                               QMAN_COMMON_CP_CGM_PWR_GATE_EN);
+                               enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
 
                qman_offset += TPC_QMAN_OFFSET;
        }
-- 
2.25.1