On Fri, 04 Sep 2020, Russ Weight wrote:
> Extend the MAX10 BMC Security Engine driver to include
> the functions that enable secure updates of BMC images,
> FPGA images, etc.
>
> Signed-off-by: Russ Weight <russell.h.wei...@intel.com>
> Reviewed-by: Wu Hao <hao...@intel.com>
> ---
> drivers/fpga/intel-m10-bmc-secure.c | 272 +++++++++++++++++++++++++++-
> include/linux/mfd/intel-m10-bmc.h | 101 +++++++++++
> 2 files changed, 372 insertions(+), 1 deletion(-)
> /**
> * struct intel_m10bmc_retimer_pdata - subdev retimer platform data
> *
> @@ -64,7 +131,10 @@ struct intel_m10bmc {
> *
> * m10bmc_raw_read - read m10bmc register per addr
> * m10bmc_raw_bulk_read - bulk_read max10 registers per addr
> + * m10bmc_raw_bulk_write - bulk_write max10 registers per addr
> + * m10bmc_raw_update_bits - update max10 register per addr
> * m10bmc_sys_read - read m10bmc system register per offset
> + * m10bmc_sys_update_bits - update max10 system register per offset
> */
> static inline int
> m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
> @@ -94,7 +164,38 @@ m10bmc_raw_bulk_read(struct intel_m10bmc *m10bmc,
> unsigned int addr,
> return ret;
> }
>
> +static inline int
> +m10bmc_raw_bulk_write(struct intel_m10bmc *m10bmc, unsigned int addr,
> + void *val, size_t cnt)
> +{
> + int ret;
> +
> + ret = regmap_bulk_write(m10bmc->regmap, addr, val, cnt);
> + if (ret)
> + dev_err(m10bmc->dev, "fail to write raw reg %x cnt %zx: %d\n",
> + addr, cnt, ret);
> +
> + return ret;
> +}
> +
> +static inline int
> +m10bmc_raw_update_bits(struct intel_m10bmc *m10bmc, unsigned int addr,
> + unsigned int msk, unsigned int val)
> +{
> + int ret;
> +
> + ret = regmap_update_bits(m10bmc->regmap, addr, msk, val);
> + if (ret)
> + dev_err(m10bmc->dev, "fail to update raw reg %x: %d\n",
> + addr, ret);
> +
> + return ret;
> +}
> +
I really do dislike abstraction for abstraction's sake.
What's stopping you from just using the Regmap API in-place?
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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