On Fri, Sep 4, 2020 at 9:55 PM Christoph Hellwig <h...@lst.de> wrote: > > On Fri, Sep 04, 2020 at 09:51:21PM +0530, Anup Patel wrote: > > The TIME CSR is usually not present on most RISC-V systems so the > > M-mode firmware will emulate the TIME CSR for the S-mode (MMU) kernel > > whereas the M-mode (NoMMU) kernel will have to use MMIO clocksource. > > > > Currently, the get_cycles() implementation in asm/timex.h does not > > consider the above fact so we provide alternate implementation of > > the get_cycles() for the M-mode (NoMMU) kernel which expects drivers > > to provide custom MMIO based read_cycles64() method. > > Please just go back to the previous working version without all the > crazy indirections. > > The whole timer and irq code has been turned into a giant maze of > indirections lately.
I respectfully disagree. IMHO, the previous code made the RISC-V timer driver convoluted (both SBI call and CLINT in one place) and mandated CLINT for NoMMU kernel. In fact, RISC-V spec does not mandate CLINT or PLIC. The RISC-V SOC vendors are free to implement their own timer device, IPI device and interrupt controller. We already have RISC-V systems (e.g. Andes AE350) where we have a different timer and IPI device instead of CLINT. The current code is more flexible and allows SOC vendors to write their own timer driver under drivers/clocksource. Regards, Anup
