On 9/3/20 20:14, Krzysztof Kozlowski wrote:
> Commit 78a68acf3d33 ("ARM: dts: exynos: Switch to dedicated Odroid XU3
> sound card binding") added assigned clocks under sound device node.
> 
> However the dtschema expects "clocks" property if "assigned-clocks" are
> used.  Add reference to input clock, the parent used in
> "assigned-clock-parents" to silence the dtschema warnings:
I'm afraid it doesn't improve anything, we just add another violation of
the DT binding rules as the 'sound' node doesn't represent a real HW and
shouldn't have 'clocks' property. Instead we could move the assigned-clock*
properties to the I2S node, as in below patch. I have tested that already 
on xu3.

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>From f98d2f5ac86d1ae13a77ef481fcbf073a1740f26 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawro...@samsung.com>
Date: Fri, 4 Sep 2020 12:02:11 +0200
Subject: [PATCH] ARM: dts: samsung: odroid-xu3: Move assigned-clock*
 properties to i2s0 node

The purpose of those assigned-clock-* properties is to configure clock for
for the I2S device so move them to respective node.

This suppresses the dtbs_check warning:
arch/arm/boot/dts/exynos5422-odroidxu3.dt.yaml: sound: 'clocks' is a dependency 
of 'assigned-clocks'

Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 60 ++++++++++-------------
 1 file changed, 27 insertions(+), 33 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi 
b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
index c3c2d85..b5ec4f4 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
@@ -29,30 +29,6 @@
                        "HiFi Playback", "Mixer DAI TX",
                        "Mixer DAI RX", "HiFi Capture";
 
-               assigned-clocks = <&clock CLK_MOUT_EPLL>,
-                               <&clock CLK_MOUT_MAU_EPLL>,
-                               <&clock CLK_MOUT_USER_MAU_EPLL>,
-                               <&clock_audss EXYNOS_MOUT_AUDSS>,
-                               <&clock_audss EXYNOS_MOUT_I2S>,
-                               <&clock_audss EXYNOS_DOUT_SRP>,
-                               <&clock_audss EXYNOS_DOUT_AUD_BUS>,
-                               <&clock_audss EXYNOS_DOUT_I2S>;
-
-               assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
-                               <&clock CLK_MOUT_EPLL>,
-                               <&clock CLK_MOUT_MAU_EPLL>,
-                               <&clock CLK_MAU_EPLL>,
-                               <&clock_audss EXYNOS_MOUT_AUDSS>;
-
-               assigned-clock-rates = <0>,
-                               <0>,
-                               <0>,
-                               <0>,
-                               <0>,
-                               <196608001>,
-                               <(196608002 / 2)>,
-                               <196608000>;
-
                cpu {
                        sound-dai = <&i2s0 0>, <&i2s0 1>;
                };
@@ -62,13 +38,6 @@
        };
 };
 
-&clock_audss {
-       assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
-                         <&clock CLK_FOUT_EPLL>;
-       assigned-clock-rates = <(196608000 / 256)>,
-                              <196608000>;
-};
-
 &hsi2c_5 {
        status = "okay";
        max98090: max98090@10 {
@@ -84,6 +53,31 @@
 
 &i2s0 {
        status = "okay";
-       assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
-       assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
+       assigned-clocks = <&clock CLK_MOUT_EPLL>,
+                       <&clock CLK_MOUT_MAU_EPLL>,
+                       <&clock CLK_MOUT_USER_MAU_EPLL>,
+                       <&clock_audss EXYNOS_MOUT_AUDSS>,
+                       <&clock_audss EXYNOS_MOUT_I2S>,
+                       <&i2s0 CLK_I2S_RCLK_SRC>,
+                       <&clock_audss EXYNOS_DOUT_SRP>,
+                       <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+                       <&clock_audss EXYNOS_DOUT_I2S>;
+
+       assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+                       <&clock CLK_MOUT_EPLL>,
+                       <&clock CLK_MOUT_MAU_EPLL>,
+                       <&clock CLK_MAU_EPLL>,
+                       <&clock_audss EXYNOS_MOUT_AUDSS>,
+                       <&clock_audss EXYNOS_SCLK_I2S>;
+
+       assigned-clock-rates = <0>,
+                       <0>,
+                       <0>,
+                       <0>,
+                       <0>,
+                       <0>,
+                       <196608001>,
+                       <(196608002 / 2)>,
+                       <196608000>;
+
 };
-- 
2.7.4

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