On 8/10/20 6:42 AM, Alexandru Ardelean wrote: > From: Mircea Caprioru <mircea.capri...@analog.com> > > All (newer) FPGA IP cores supported by Analog Devices, store information in > the synthesized designs. This information describes various parameters, > including the family of boards on which this is deployed, speed-grade, and > so on. > > Currently, some of these definitions are deployed mostly on Xilinx boards, > but they have been considered also for FPGA boards from other vendors. > > The register definitions are described at this link: > https://wiki.analog.com/resources/fpga/docs/hdl/regmap > (the 'Base (common to all cores)' section). > > Signed-off-by: Mircea Caprioru <mircea.capri...@analog.com> > Signed-off-by: Alexandru Ardelean <alexandru.ardel...@analog.com>
Thanks for changes. Reviewed-by: Tom Rix <t...@redhat.com> > --- > include/linux/fpga/adi-axi-common.h | 103 ++++++++++++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/include/linux/fpga/adi-axi-common.h > b/include/linux/fpga/adi-axi-common.h > index 141ac3f251e6..5c7d212a5d4a 100644 > --- a/include/linux/fpga/adi-axi-common.h > +++ b/include/linux/fpga/adi-axi-common.h > @@ -13,6 +13,9 @@ > > #define ADI_AXI_REG_VERSION 0x0000 > > +#define ADI_AXI_REG_FPGA_INFO 0x001C > +#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140 > + > #define ADI_AXI_PCORE_VER(major, minor, patch) \ > (((major) << 16) | ((minor) << 8) | (patch)) > > @@ -20,4 +23,104 @@ > #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) > #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) > > +#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff) > + > +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) > +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) > +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) > +#define ADI_AXI_INFO_FPGA_DEV_PACKAGE(info) ((info) & 0xff) > + > +/** > + * FPGA Technology definitions > + */ > +#define ADI_AXI_FPGA_TECH_XILINX_UNKNOWN 0 > +#define ADI_AXI_FPGA_TECH_XILINS_SERIES7 1 > +#define ADI_AXI_FPGA_TECH_XILINX_ULTRASCALE 2 > +#define ADI_AXI_FPGA_TECH_XILINX_ULTRASCALE_PLUS 3 > + > +#define ADI_AXI_FPGA_TECH_INTEL_UNKNOWN 100 > +#define ADI_AXI_FPGA_TECH_INTEL_CYCLONE_5 101 > +#define ADI_AXI_FPGA_TECH_INTEL_CYCLONE_10 102 > +#define ADI_AXI_FPGA_TECH_INTEL_ARRIA_10 103 > +#define ADI_AXI_FPGA_TECH_INTEL_STRATIX_10 104 > + > +/** > + * FPGA Family definitions > + */ > +#define ADI_AXI_FPGA_FAMILY_UNKNOWN 0 > + > +#define ADI_AXI_FPGA_FAMILY_XILINX_ARTIX 1 > +#define ADI_AXI_FPGA_FAMILY_XILINX_KINTEX 2 > +#define ADI_AXI_FPGA_FAMILY_XILINX_VIRTEX 3 > +#define ADI_AXI_FPGA_FAMILY_XILINX_ZYNQ 4 > + > +#define ADI_AXI_FPGA_FAMILY_INTEL_SX 1 > +#define ADI_AXI_FPGA_FAMILY_INTEL_GX 2 > +#define ADI_AXI_FPGA_FAMILY_INTEL_GT 3 > +#define ADI_AXI_FPGA_FAMILY_INTEL_GZ 4 > + > +/** > + * FPGA Speed-grade definitions > + */ > +#define ADI_AXI_FPGA_SPEED_GRADE_UNKNOWN 0 > + > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1 10 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1L 11 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1H 12 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1HV 13 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1LV 14 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2 20 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2L 21 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2LV 22 > +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_3 30 > + > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_1 1 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_2 2 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_3 3 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_4 4 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_5 5 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_6 6 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_7 7 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_8 8 > +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_9 9 > + > +/** > + * FPGA Device Package definitions > + */ > +#define ADI_AXI_FPGA_DEV_PACKAGE_UNKNOWN 0 > + > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RF 1 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FL 2 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FF 3 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FB 4 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_HC 5 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FH 6 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CS 7 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CP 8 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FT 9 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FG 10 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_SB 11 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RB 12 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RS 13 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CL 14 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_SF 15 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_BA 16 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FA 17 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FS 18 > +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FI 19 > + > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_BGA 1 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PGA 2 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_FBGA 3 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_HBGA 4 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PDIP 5 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_EQFP 6 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PLCC 7 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PQFP 8 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_RQFP 9 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_TQFP 10 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_UBGA 11 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_UFBGA 12 > +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_MBGA 13 > + > #endif /* ADI_AXI_COMMON_H_ */
