tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 449dc8c97089a6e09fb2dac4d92b1b7ac0eb7c1e commit: d82bcef5157de1368c08244a846ab968b3e5cb7e soc: imx: select ARM_GIC_V3 for i.MX8M date: 4 weeks ago config: arm-randconfig-p002-20200808 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout d82bcef5157de1368c08244a846ab968b3e5cb7e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <l...@intel.com>
All errors (new ones prefixed by >>):
In file included from include/linux/irqchip/arm-gic-v3.h:662,
from drivers/irqchip/irq-gic-v3.c:24:
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_PMR_EL1':
>> arch/arm/include/asm/arch_gicv3.h:44:2: error: implicit declaration of
>> function 'write_sysreg' [-Werror=implicit-function-declaration]
44 | write_sysreg(val, a32); \
| ^~~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:51:1: note: in expansion of macro
'CPUIF_MAP'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:22:20: error: implicit declaration of
>> function '__ACCESS_CP15' [-Werror=implicit-function-declaration]
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~~~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:22:34: error: 'c4' undeclared (first use
>> in this function)
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
arch/arm/include/asm/arch_gicv3.h:22:34: note: each undeclared identifier is
reported only once for each function it appears in
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:22:41: error: 'c6' undeclared (first use
>> in this function)
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_PMR_EL1':
>> arch/arm/include/asm/arch_gicv3.h:48:9: error: implicit declaration of
>> function 'read_sysreg' [-Werror=implicit-function-declaration]
48 | return read_sysreg(a32); \
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:51:1: note: in expansion of macro
'CPUIF_MAP'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:22:34: error: 'c4' undeclared (first use
>> in this function)
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:22:41: error: 'c6' undeclared (first use
>> in this function)
22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro
'ICC_PMR'
51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
| ^~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R0_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro
'__ICC_AP0Rx'
30 | #define ICC_AP0R0 __ICC_AP0Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro
'ICC_AP0R0'
52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro
'__ICC_AP0Rx'
30 | #define ICC_AP0R0 __ICC_AP0Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro
'ICC_AP0R0'
52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R0_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro
'__ICC_AP0Rx'
30 | #define ICC_AP0R0 __ICC_AP0Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro
'ICC_AP0R0'
52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro
'__ICC_AP0Rx'
30 | #define ICC_AP0R0 __ICC_AP0Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro
'ICC_AP0R0'
52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R1_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro
'__ICC_AP0Rx'
31 | #define ICC_AP0R1 __ICC_AP0Rx(1)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro
'ICC_AP0R1'
53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro
'__ICC_AP0Rx'
31 | #define ICC_AP0R1 __ICC_AP0Rx(1)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro
'ICC_AP0R1'
53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R1_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro
'__ICC_AP0Rx'
31 | #define ICC_AP0R1 __ICC_AP0Rx(1)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro
'ICC_AP0R1'
53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro
'__ICC_AP0Rx'
31 | #define ICC_AP0R1 __ICC_AP0Rx(1)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro
'ICC_AP0R1'
53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R2_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro
'__ICC_AP0Rx'
32 | #define ICC_AP0R2 __ICC_AP0Rx(2)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro
'ICC_AP0R2'
54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro
'__ICC_AP0Rx'
32 | #define ICC_AP0R2 __ICC_AP0Rx(2)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro
'ICC_AP0R2'
54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R2_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro
'__ICC_AP0Rx'
32 | #define ICC_AP0R2 __ICC_AP0Rx(2)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro
'ICC_AP0R2'
54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
| ^~~~~~~~~
>> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
>> in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro
'__ICC_AP0Rx'
32 | #define ICC_AP0R2 __ICC_AP0Rx(2)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro
'ICC_AP0R2'
54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R3_EL1':
>> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
>> in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro
'__ICC_AP0Rx'
33 | #define ICC_AP0R3 __ICC_AP0Rx(3)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro
'ICC_AP0R3'
55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro
'__ICC_AP0Rx'
33 | #define ICC_AP0R3 __ICC_AP0Rx(3)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro
'ICC_AP0R3'
55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R3_EL1':
arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use
in this function)
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro
'__ICC_AP0Rx'
33 | #define ICC_AP0R3 __ICC_AP0Rx(3)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro
'ICC_AP0R3'
55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use
in this function); did you mean 'u8'?
29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro
'__ICC_AP0Rx'
33 | #define ICC_AP0R3 __ICC_AP0Rx(3)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro
'ICC_AP0R3'
55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP1R0_EL1':
arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use
in this function)
35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro
'__ICC_AP1Rx'
36 | #define ICC_AP1R0 __ICC_AP1Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro
'ICC_AP1R0'
56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:35:48: error: 'c9' undeclared (first use
in this function)
35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
| ^~
arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro
'CPUIF_MAP'
44 | write_sysreg(val, a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro
'__ICC_AP1Rx'
36 | #define ICC_AP1R0 __ICC_AP1Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro
'ICC_AP1R0'
56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP1R0_EL1':
arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use
in this function)
35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
| ^~~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro
'__ICC_AP1Rx'
36 | #define ICC_AP1R0 __ICC_AP1Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro
'ICC_AP1R0'
56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:35:48: error: 'c9' undeclared (first use
in this function)
35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
| ^~
arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro
'CPUIF_MAP'
48 | return read_sysreg(a32); \
| ^~~
arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro
'__ICC_AP1Rx'
36 | #define ICC_AP1R0 __ICC_AP1Rx(0)
| ^~~~~~~~~~~
arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro
'ICC_AP1R0'
56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
| ^~~~~~~~~
arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP1R1_EL1':
arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use
in this function)
..
vim +/write_sysreg +44 arch/arm/include/asm/arch_gicv3.h
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 17
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 18 #define ICC_EOIR1
__ACCESS_CP15(c12, 0, c12, 1)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 @19 #define ICC_DIR
__ACCESS_CP15(c12, 0, c11, 1)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 20 #define ICC_IAR1
__ACCESS_CP15(c12, 0, c12, 0)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 @21 #define ICC_SGI1R
__ACCESS_CP15_64(0, c12)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 @22 #define ICC_PMR
__ACCESS_CP15(c4, 0, c6, 0)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 23 #define ICC_CTLR
__ACCESS_CP15(c12, 0, c12, 4)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 24 #define ICC_SRE
__ACCESS_CP15(c12, 0, c12, 5)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 25 #define ICC_IGRPEN1
__ACCESS_CP15(c12, 0, c12, 7)
91ef84428a86b7 Daniel Thompson 2016-08-19 26 #define ICC_BPR1
__ACCESS_CP15(c12, 0, c12, 3)
e99da7c6f51b48 Julien Thierry 2019-01-31 27 #define ICC_RPR
__ACCESS_CP15(c12, 0, c11, 3)
d5cd50d318f70f Jean-Philippe Brucker 2015-10-01 28
d6062a6d62c643 Marc Zyngier 2018-03-09 @29 #define __ICC_AP0Rx(x)
__ACCESS_CP15(c12, 0, c8, 4 | x)
d6062a6d62c643 Marc Zyngier 2018-03-09 30 #define ICC_AP0R0
__ICC_AP0Rx(0)
d6062a6d62c643 Marc Zyngier 2018-03-09 31 #define ICC_AP0R1
__ICC_AP0Rx(1)
d6062a6d62c643 Marc Zyngier 2018-03-09 32 #define ICC_AP0R2
__ICC_AP0Rx(2)
d6062a6d62c643 Marc Zyngier 2018-03-09 33 #define ICC_AP0R3
__ICC_AP0Rx(3)
d6062a6d62c643 Marc Zyngier 2018-03-09 34
d6062a6d62c643 Marc Zyngier 2018-03-09 @35 #define __ICC_AP1Rx(x)
__ACCESS_CP15(c12, 0, c9, x)
d6062a6d62c643 Marc Zyngier 2018-03-09 36 #define ICC_AP1R0
__ICC_AP1Rx(0)
d6062a6d62c643 Marc Zyngier 2018-03-09 37 #define ICC_AP1R1
__ICC_AP1Rx(1)
d6062a6d62c643 Marc Zyngier 2018-03-09 38 #define ICC_AP1R2
__ICC_AP1Rx(2)
d6062a6d62c643 Marc Zyngier 2018-03-09 39 #define ICC_AP1R3
__ICC_AP1Rx(3)
d6062a6d62c643 Marc Zyngier 2018-03-09 40
a078bedf17c2e4 Vladimir Murzin 2016-09-12 41 #define CPUIF_MAP(a32,
a64) \
a078bedf17c2e4 Vladimir Murzin 2016-09-12 42 static inline void write_
## a64(u32 val) \
a078bedf17c2e4 Vladimir Murzin 2016-09-12 43 {
\
a078bedf17c2e4 Vladimir Murzin 2016-09-12 @44 write_sysreg(val, a32);
\
a078bedf17c2e4 Vladimir Murzin 2016-09-12 45 }
\
a078bedf17c2e4 Vladimir Murzin 2016-09-12 46 static inline u32 read_ ##
a64(void) \
a078bedf17c2e4 Vladimir Murzin 2016-09-12 47 {
\
a078bedf17c2e4 Vladimir Murzin 2016-09-12 @48 return
read_sysreg(a32); \
a078bedf17c2e4 Vladimir Murzin 2016-09-12 49 }
\
a078bedf17c2e4 Vladimir Murzin 2016-09-12 50
:::::: The code at line 44 was first introduced by commit
:::::: a078bedf17c2e43819fea54bdfd5793845142e3a ARM: gic-v3: Introduce
32-to-64-bit mappings for GICv3 cpu registers
:::::: TO: Vladimir Murzin <vladimir.mur...@arm.com>
:::::: CC: Christoffer Dall <christoffer.d...@linaro.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
