On Tue, Jun 16, 2020 at 06:26:54PM +0530, Bharat Kumar Gogada wrote:
> - Add support for Versal CPM as Root Port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
>   block for CPM along with the integrated bridge can function
>   as PCIe Root Port.
> - Bridge error and legacy interrupts in Versal CPM are handled using
>   Versal CPM specific interrupt line.

> +static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie_port *port)
> +{
> +     if (cpm_pcie_link_up(port))
> +             dev_info(port->dev, "PCIe Link is UP\n");
> +     else
> +             dev_info(port->dev, "PCIe Link is DOWN\n");
> +
> +     /* Disable all interrupts */
> +     pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
> +                XILINX_CPM_PCIE_REG_IMR);
> +
> +     /* Clear pending interrupts */
> +     pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) &
> +                XILINX_CPM_PCIE_IMR_ALL_MASK,
> +                XILINX_CPM_PCIE_REG_IDR);
> +
> +     /*
> +      * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> +      * CPM SLCR block.
> +      */
> +     writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
> +            port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> +     /* Enable the Bridge enable bit */
> +     pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
> +                XILINX_CPM_PCIE_REG_RPSC_BEN,
> +                XILINX_CPM_PCIE_REG_RPSC);
> +}
> +
> +/**
> + * xilinx_cpm_pcie_parse_dt - Parse Device tree
> + * @port: PCIe port information
> + * @bus_range: Bus resource
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie_port *port,
> +                                 struct resource *bus_range)
> +{
> +     struct device *dev = port->dev;
> +     struct platform_device *pdev = to_platform_device(dev);
> +     struct resource *res;
> +
> +     port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
> +                                                            "cpm_slcr");
> +     if (IS_ERR(port->cpm_base))
> +             return PTR_ERR(port->cpm_base);
> +
> +     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> +     if (!res)
> +             return -ENXIO;
> +
> +     port->cfg = pci_ecam_create(dev, res, bus_range,
> +                                 &pci_generic_ecam_ops);

Aren't we passing an uninitialized pointer (bus_range) here?  This
looks broken to me.

The kernelci build warns about it:
https://kernelci.org/build/next/branch/master/kernel/next-20200805/

  /scratch/linux/drivers/pci/controller/pcie-xilinx-cpm.c:557:39: warning: 
variable 'bus_range' is uninitialized when used here [-Wuninitialized]

I'm dropping this for now.  I can't believe this actually works.

Bjorn

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