[PATCH 7/7] arm64: dts: qcom: sm8250: Add EPSS L3 interconnect provider

[Sibi Sankar]

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SM8250
SoCs.

Signed-off-by: Sibi Sankar <si...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 73f02f712d035..2bcdb7a3b9fef 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -2150,6 +2151,16 @@ apps_bcm_voter: bcm_voter {
                                compatible = "qcom,bcm-voter";
                        };
                };
+
+               epss_l3: interconnect@18591000 {
+                       compatible = "qcom,sm8250-epss-l3";
+                       reg = <0 0x18590000 0 0x1000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #interconnect-cells = <1>;
+               };
        };
 
        timer {
-- 
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