On Tue, Jul 14, 2020 at 12:02:09AM -0700, ira.we...@intel.com wrote: > From: Ira Weiny <ira.we...@intel.com> > > The PKRS MSR is defined as a per-core register. This isolates memory > access by CPU. Unfortunately, the MSR is not preserved by XSAVE. > Therefore, We must preserve the protections for individual tasks even if > they are context switched out and placed on another cpu later.
This is a contradiction and utter trainwreck. We're not going to do more per-core MSRs and pretend they make sense per-task.
