2007/10/25, Chuck Ebbert <[EMAIL PROTECTED]>: > On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote: > >>> > >>> I fill something wrong here. > >>> Is it possible to reduce the amount of timer interrupts? > >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled? > >>> > >> How are you disabling C1E? > >> > >> > > dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic > > initialization code. I make it for test purpose only, so i do not produce a > > patch. > > > > Why does disabling C1E disable C1, C2 and C3?
i don't know. Normally (C1E enabled) i have C1 power state only. When I disable C1E, i have no any power state (AMD spec say i should have C1 and C2; C3 is optional) > Thomas, in the case of the machines where C1E is disabled on CPU 0 but > enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the > vendor just forgot to disable CPU 1... - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
