Tx-only DMA transfers are working perfectly fine since in this case
the code just ignores the Rx FIFO overflow interrupts. But it turns
out the SPI Rx-only transfers are broken since nothing pushing any
data to the shift registers, so the Rx FIFO is left empty and the
SPI core subsystems just returns a timeout error. Since DW DMAC
driver doesn't support something like cyclic write operations of
a single byte to a device register, the only way to support the
Rx-only SPI transfers is to fake it by using a dummy Tx-buffer.
This is what we intend to fix in this commit by setting the
SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.
Signed-off-by: Serge Semin <sergey.se...@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Cc: Georgy Vlasov <georgy.vla...@baikalelectronics.ru>
Cc: Ramil Zaripov <ramil.zari...@baikalelectronics.ru>
Cc: Alexey Malahov <alexey.mala...@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbog...@alpha.franken.de>
Cc: Arnd Bergmann <a...@arndb.de>
Cc: Feng Tang <feng.t...@intel.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
drivers/spi/spi-dw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 6939e003e3e9..4d1849699a12 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -515,6 +515,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
dev_warn(dev, "DMA init failed\n");
} else {
master->can_dma = dws->dma_ops->can_dma;
+ master->flags |= SPI_CONTROLLER_MUST_TX;
}
}
--
2.26.2
