On Thu, May 14, 2020 at 11:12:01PM +0200, Arnd Bergmann wrote: > On Thu, May 14, 2020 at 6:25 PM Russell King - ARM Linux admin > <li...@armlinux.org.uk> wrote: > > On Thu, May 14, 2020 at 02:41:11PM +0200, Arnd Bergmann wrote: > > > On Thu, May 14, 2020 at 1:18 PM afzal mohammed <afzal.mohd...@gmail.com> > > > wrote: > > > > It's clearly possible to do something very similar for older chips > > > (v6 or v7 without LPAE, possibly even v5), it just gets harder > > > while providing less benefit. > > > > Forget about doing this for anything without a PIPT cache - or you're > > going to end up having to flush the data cache each time you enter or > > exit the kernel. > > Right, let's forget I said anything about v5 or earlier ;-) > > I expected the non-aliasing VIPT caches to work the same as PIPT, can > you clarify if there is something to be aware of for those? I see that some > ARMv8 chips and most ARMv6 chips (not OMAP2 and Realview) are > of that kind, and at we clearly don't want to break running on ARMv8 at > least.
There are some aliasing VIPT implementations on ARMv6, but I don't remember how common. > Anyway my point was that it's best to only do it for LPAE anyway, everything > else being a distraction, as the only non-LPAE SoCs I could find with > support for over 2GB are some of the higher-end i.MX6 versions and the > original highbank. Yep. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up
