mfgcfg clock is under MFG_ASYNC power domain

Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5dce7d6..ca865ab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -707,6 +707,7 @@
                        compatible = "mediatek,mt8183-mfgcfg", "syscon";
                        reg = <0 0x13000000 0 0x1000>;
                        #clock-cells = <1>;
+                       power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
                };
 
                mmsys: syscon@14000000 {
-- 
1.8.1.1.dirty

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