Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sdm845

Signed-off-by: Rajendra Nayak <rna...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 67e3b90..1843123 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3017,6 +3017,30 @@
                        status = "disabled";
                };
 
+               qspi_opp_table: qspi-opp-table {
+                       compatible = "operating-points-v2";
+
+                       opp-19200000 {
+                               opp-hz = /bits/ 64 <19200000>;
+                               required-opps = <&rpmhpd_opp_min_svs>;
+                       };
+
+                       opp-100000000 {
+                               opp-hz = /bits/ 64 <100000000>;
+                               required-opps = <&rpmhpd_opp_low_svs>;
+                       };
+
+                       opp-150000000 {
+                               opp-hz = /bits/ 64 <150000000>;
+                               required-opps = <&rpmhpd_opp_svs>;
+                       };
+
+                       opp-300000000 {
+                               opp-hz = /bits/ 64 <300000000>;
+                               required-opps = <&rpmhpd_opp_nom>;
+                       };
+               };
+
                qspi: spi@88df000 {
                        compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
                        reg = <0 0x088df000 0 0x600>;
@@ -3026,6 +3050,8 @@
                        clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
                                 <&gcc GCC_QSPI_CORE_CLK>;
                        clock-names = "iface", "core";
+                       power-domains = <&rpmhpd SDM845_CX>;
+                       operating-points-v2 = <&qspi_opp_table>;
                        status = "disabled";
                };
 
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