Hi Prabhakar,
On Mon, Apr 27, 2020 at 4:41 PM Lad Prabhakar
<prabhakar.mahadev-lad...@bp.renesas.com> wrote:
> Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu
> <marian-cristian.rotariu...@bp.renesas.com>
> ---
> Changes for v2:
> * Dropped zt* clocks
> * lb clock is now a base clock
> * Fixed clock-sources for scif2/sdhi1/iic2
> * Dropped setting div to 3 for zg clock
Thanks for the update
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
> +static struct cpg_core_clk r8a7742_core_clks[] __initdata = {
Missing "const".
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
i.e. will queue in clk-renesas-for-v5.8, with the above fixed (i.e. no need to
resend).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
