On Tue, Sep 17, 2019 at 3:26 PM Paul Walmsley <paul.walms...@sifive.com> wrote:
>
>
> Just tested this on the SiFive HiFive Unleashed. Seems to work OK;
> however I did not stress-test it.
>
> Tested-by: Paul Walmsley <paul.walms...@sifive.com> # HiFive Unleashed
>
>
> - Paul
>
>
> # !cat
> cat /proc/interrupts
> CPU0 CPU1 CPU2 CPU3
> 1: 0 0 0 0 SiFive PLIC 5
> 10011000.serial
> 3: 0 0 0 0 SiFive PLIC 51
> 10040000.spi
> 4: 6266 0 0 0 SiFive PLIC 4
> 10010000.serial
> 5: 102 0 0 0 SiFive PLIC 6
> 10050000.spi
> 6: 37 0 0 0 SiFive PLIC 53 eth0
> IPI0: 1134 21128 9024 220261 Rescheduling interrupts
> IPI1: 10 143 18 7 Function call interrupts
> IPI2: 0 0 0 0 CPU stop interrupts
> #
I have applied the patch on top of 5.2.9 kernel and tried to stress it
with stress-ng interrupt stressors for 2:30+ hours.
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 0 0 0 0 SiFive PLIC 5
10011000.serial
3: 0 0 0 0 SiFive PLIC 51 10040000.spi
4: 34240 0 0 0 SiFive PLIC 4
10010000.serial
5: 102 0 0 0 SiFive PLIC 6 10050000.spi
6: 0 0 0 0 SiFive PLIC 53 eth0
7: 0 0 0 0 SiFive PLIC 32
microsemi-pcie
IPI0: 32013933 28068736 29345256 23346339 Rescheduling interrupts
IPI1: 78514 78586 63144 100317 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
