Support of boot-time switching between 4- and 5-level paging mode is
upstream since 4.17.
We run internal testing with 5-level paging support enabled for a while
and it doesn't not cause any functional or performance regression on
4-level paging hardware.
The only 5-level paging related regressions I saw were in early boot
code that runs independently from CONFIG_X86_5LEVEL.
The next major release of distributions expected to have
CONFIG_X86_5LEVEL=y.
Enable the option by default. It may help to catch obscure bugs early.
Signed-off-by: Kirill A. Shutemov <kirill.shute...@linux.intel.com>
---
arch/x86/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 222855cc0158..2f7cb91d850e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1483,6 +1483,7 @@ config X86_PAE
config X86_5LEVEL
bool "Enable 5-level page tables support"
+ default y
select DYNAMIC_MEMORY_LAYOUT
select SPARSEMEM_VMEMMAP
depends on X86_64
--
2.21.0
