From: Voon Weifeng <weifeng.v...@intel.com> Date: Tue, 27 Aug 2019 09:38:07 +0800
> In order to keep PCI info simple and neat, this patch series have > introduced a 3 hierarchy of struct. First layer will be the > intel_mgbe_common_data struct which keeps all Intel common configuration. > Second layer will be xxx_common_data which keeps all the different Intel > microarchitecture, e.g tgl, ehl. The third layer will be configuration > that tied to the PCI ID only based on speed and RGMII/SGMII interface. > > EHL and TGL will also having a higher system clock which is 200Mhz. Series applied.
