> -----Original Message-----
> From: Ashish Kumar <ashish.ku...@nxp.com>
> Sent: Tuesday, August 13, 2019 4:08 PM
> To: tudor.amba...@microchip.com; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com;
> miquel.ray...@bootlin.com; rich...@nod.at; vigne...@ti.com; linux-
> m...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org; Ashish Kumar <ashish.ku...@nxp.com>;
> Kuldeep Singh <kuldeep.si...@nxp.com>; Ashish Kumar
> <ashish.ku...@nxp.com>
> Subject: [Patch v3] drivers: mtd: spi-nor: Add flash property for mt25qu512a
> and mt35xu02g
Hi Vignesh, Tudor Ambarus,
Could you please update, if there are any further comments on this patch.
Regards
Ashish
>
> mt25qu512a is rebranded after its spinoff from STM, so it is different only in
> term of operating frequency, initial JEDEC id is same as that of n25q512a. In
> order to avoid any confussion with respect to name new entry is added.
> This flash is tested for Single I/O and QUAD I/O mode on LS1046FRWY.
>
> mt35xu02g is Octal flash supporting Single I/O and QCTAL I/O and it has been
> tested on LS1028ARDB
>
> Signed-off-by: Kuldeep Singh <kuldeep.si...@nxp.com>
> Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com>
> ---
> v3:
> -Reword commits msg
> -rebase to top of mtd-linux spi-nor/next
> v2:
> Incorporate review comments from Vignesh
>
> drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 03cc788..97d3de8 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1988,6 +1988,12 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> +
> + /* Micron */
> + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
> SECT_4K |
> + USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
> +
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> @@ -2003,6 +2009,9 @@ static const struct flash_info spi_nor_ids[] = {
> SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
> SPI_NOR_4B_OPCODES)
> },
> + { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
> + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
> + SPI_NOR_4B_OPCODES) },
>
> /* PMC */
> { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
> --
> 2.7.4
