Em Mon, 19 Aug 2019 08:26:19 +0200 Christoph Hellwig <h...@lst.de> escreveu:
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote: > > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote: > > > The sifive_l2_cache.c is in no way related to RISC-V architecture > > > memory management. It is a little stub driver working around the fact > > > that the EDAC maintainers prefer their drivers to be structured in a > > > certain way > > > > That changed recently so I guess we can do the per-IP block driver after > > all, if people would still prefer it. > > That would seem like the best idea. But I don't really know this code > well enough myself, and I really need to get this code out of the > forced on RISC-V codebase as some SOCs I'm working with simply don't > have the memory for it.. > > So unless someone signs up to do a per-IP block edac drivers instead > very quickly I'd still like to see something like this go into 5.4 > for now. I'm wandering if we should at least add an entry for this one at MAINTAINERS, pointing it to the EDAC mailing list. Something like: diff --git a/MAINTAINERS b/MAINTAINERS index 7dfe381c8b43..1c3bc5aa3af0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5906,6 +5906,7 @@ M: Yash Shah <yash.s...@sifive.com> L: linux-e...@vger.kernel.org S: Supported F: drivers/edac/sifive_edac.c +F: drivers/soc/sifive/ EDAC-SKYLAKE M: Tony Luck <tony.l...@intel.com> Thanks, Mauro
