Hi Fancy,
On Wed, 2019-06-26 at 06:46 +0000, Fancy Fang wrote:
> Hi Philipp,
>
> Thanks for your comments. And please see my answers below.
>
[...]
> > +Specifying sft-rstn control of devices
> > +======================================
> > +
> > +Device nodes in Display Mix should specify the reset channel required
> > +in their "resets" property, containing a phandle to the sft-rstn
> > +device node and an index to specify which channel to use, as
> > +described in Documentation/devicetree/bindings/reset/reset.txt.
> > +
> > +example:
> > +
> > + lcdif_resets: lcdif-resets {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #reset-cells = <0>;
> > +
> > + lcdif-soft-resetn {
> > + compatible = "lcdif,soft-resetn";
> > + resets = <&dispmix_sft_rstn
> > IMX8MN_LCDIF_APB_CLK_RESET>,
> > + <&dispmix_sft_rstn
> > + IMX8MN_LCDIF_PIXEL_CLK_RESET>;
>
> From these names, on i.MX8MN these look like they could be an internal
> property of the DISPMIX clocks provided to the submodules. But on i.MX8MM the
> soft reset bits do look like actual module resets. Can you confirm whether
> this is true?
> [FF] I'll check this with the IC designer, and I'll let you know the result
> when I get the answer.
Did you get some feedback on what these resets actually are?
I'm asking because I'm wondering about how to best support VPUMIX for
the three VPU cores on i.MX8MM. The VPUMIX seems to have a SOFT_RESET
register and a CLOCK_ENABLE register, each with three bits, one bit for
each VPU. I'd be interested in knowing what these actually reset / gate
as well.
regards
Philipp
