Please do not drop it. Compressed instruction extension has some specific overhead in small RISC-V FPGA softcore, especialy in the ones which can't implement the register file read in a asynchronous manner because of the FPGA technology. What are reasons to enforce RVC ?
On Wed, Aug 7, 2019 at 2:29 PM Bin Meng <bmeng...@gmail.com> wrote: > > On Wed, Aug 7, 2019 at 10:30 AM Paul Walmsley <paul.walms...@sifive.com> > wrote: > > > > > > The baseline ISA support requirement for the RISC-V Linux kernel > > mandates compressed instructions, so it doesn't make sense for > > compressed instruction support to be configurable. > > > > Signed-off-by: Paul Walmsley <paul.walms...@sifive.com> > > Cc: Atish Patra <atish.pa...@wdc.com> > > > > --- > > arch/riscv/Kconfig | 10 ---------- > > arch/riscv/Makefile | 2 +- > > 2 files changed, 1 insertion(+), 11 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng...@gmail.com> > > _______________________________________________ > linux-riscv mailing list > linux-ri...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
