On Saturday 08 September 2007 20:29, Alan Cox wrote: > On Fri, 7 Sep 2007 15:26:50 -0700 > > Jesse Barnes <[EMAIL PROTECTED]> wrote: > > FYI, we just released a new white paper describing memory ordering for > > Intel processors: > > http://developer.intel.com/products/processor/manuals/index.htm > > > > Should help answer some questions about some of the ordering primitives > > we use on i386 and x86_64. > > Nice - but it appears to be 64bit only - and indeed it appears to be > untrue for real 32bit because of the Pentium Pro fencing errata.
As I said, we're not doing anything special in barriers for the ppro errata today anyway. > The kernel also runs on IDT Winchip, Cyrix and AMD processors not all of > which have exactly the same behaviour (the IDT Winchip as we run it > profoundly differs) AMD processors guarantee loads are ordered and stores are ordered (with exceptions of non-temporal, and non-wb policy). As for the others that do out of order stores, are any of them SMP? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
