Currently, there is no CPU topology defined for RISC-V. The following series adds topology support in RISC-V.
http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html Add a DT node for unleashed that describes the CPU topology present in HiFive Unleashed. Signed-off-by: Atish Patra <atish.pa...@wdc.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 83f40b00ab63..907564f4f07a 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -22,6 +22,24 @@ #address-cells = <1>; #size-cells = <0>; timebase-frequency = <1000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu1>; + }; + core1 { + cpu = <&cpu2>; + }; + core2 { + cpu = <&cpu3>; + }; + core3 { + cpu = <&cpu4>; + }; + }; + }; + cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; -- 2.21.0
