On Fri, 7 Jun 2019 at 06:32, Richard Cochran <richardcoch...@gmail.com> wrote: > > On Thu, Jun 06, 2019 at 04:40:19PM +0300, Vladimir Oltean wrote: > > Plain and simply because it doesn't work very well. > > Even phc2sys from the system clock to the hardware (no timestamps > > involved) has trouble staying put (under 1000 ns offset). > > And using the hardware-corrected timestamps triggers a lot of clockchecks. > > It sounds like a bug in reading or adjusting the HW clock. Is the HW > clock stable when you don't adjust its frequency?
How can I tell that for sure? > > Thanks, > Richard
