On Mon, May 27, 2019 at 10:06:07AM +0800, Shaokun Zhang wrote: > Add coherency_max_size variable to record the maximum cache line size > for different cache levels. We will synchronize it with CTR_EL0.CWG > reporting in cache_line_size() for arm64. > > Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org> > Cc: "Rafael J. Wysocki" <raf...@kernel.org> > Cc: Sudeep Holla <sudeep.ho...@arm.com> > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Jeremy Linton <jeremy.lin...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> > --- > ChangeLog since v2: > -- Rebase to 5.2-rc2 > -- Export cache_line_size for I/O driver > ChangeLog since v1: > -- Move coherency_max_size to drivers/base/cacheinfo.c > -- Address Catalin's comments > Link: https://www.spinics.net/lists/arm-kernel/msg723615.html > > drivers/base/cacheinfo.c | 5 +++++ > include/linux/cacheinfo.h | 2 ++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index a7359535caf5..8827c60f51e2 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu) > return -ENOTSUPP; > } > > +unsigned int coherency_max_size;
Why are you creating a global variable? Where are the other patches in this series? thanks, greg k-h
