On 6/05/19 8:01 PM, Scott Branden wrote:
> From: Trac Hoang <trac.ho...@broadcom.com>
>
> The iproc host eMMC/SD controller hold time does not meet the
> specification in the HS50 mode. This problem can be mitigated
> by disabling the HISPD bit; thus forcing the controller output
> data to be driven on the falling clock edges rather than the
> rising clock edges.
>
> This change applies only to the Cygnus platform.
>
> Fixes: c833e92bbb60 ("mmc: sdhci-iproc: support standard byte register
> accesses")
> Signed-off-by: Trac Hoang <trac.ho...@broadcom.com>
> Signed-off-by: Scott Branden <scott.bran...@broadcom.com>
Acked-by: Adrian Hunter <adrian.hun...@intel.com>
> ---
> drivers/mmc/host/sdhci-iproc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
> index 9d12c06c7fd6..9d4071c41c94 100644
> --- a/drivers/mmc/host/sdhci-iproc.c
> +++ b/drivers/mmc/host/sdhci-iproc.c
> @@ -196,7 +196,8 @@ static const struct sdhci_ops sdhci_iproc_32only_ops = {
> };
>
> static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
> - .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
> + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> + SDHCI_QUIRK_NO_HISPD_BIT,
> .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
> .ops = &sdhci_iproc_32only_ops,
> };
>
