From: Jerome Glisse
> Sent: 16 April 2019 16:33
...
> I am no expert but i am guessing your FPGA set the request field in the
> PCIE TLP write packet to 00:00.0 and this might work when IOMMU is off but
> might not work when IOMMU is on ie when IOMMU is on your device should set
> the request field to the FPGA PCIE id so that the IOMMU knows for which
> device the PCIE write or read packet is and thus against which IOMMU page
> table.
Interesting.
Does that mean that a malicious PCIe device can send write TLP
that contain the 'wrong' id (IIRC that is bus:dev:fn) and so
write to areas that it shouldn't access?
For any degree of security the PCIe bridge nearest the target
needs to verify the id as well.
Actually all bridges need to verify the 'bus' part.
Then boards with 'dodgy' bridges can only write to locations
that other dev:fn on the same board can access.
David
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