Please check the definition of "cache coherence".
Which of the twelve thousand such definitions? :-)
Summary: the CPU is indeed within its rights to execute loads and
stores
to a single variable out of order, -but- only if it gets the same
result
that it would have obtained by executing them in order. Which means
that
any reordering of accesses by a single CPU to a single variable will be
invisible to the software.
I'm still not sure if that applies to all architectures.
Doesn't matter anyway, let's kill this thread :-)
Segher
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