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Best Regards!
Anson Huang
> -----Original Message-----
> From: Anson Huang
> Sent: 2019年2月28日 16:56
> To: mturque...@baylibre.com; sb...@kernel.org; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> robh...@kernel.org; mark.rutl...@arm.com; Aisheng Dong
> <aisheng.d...@nxp.com>; gust...@embeddedor.com; linux-
> c...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org
> Cc: dl-linux-imx <linux-...@nxp.com>
> Subject: [PATCH 1/2] clk: imx7ulp: remove snvs clock
>
> Since i.MX7ULP B0 chip, the SNVS module is moved into M4 domain and its
> clock is also moved into PCC0 which is contorlled by M4, Linux kernel should
> NOT add it into clock tree.
>
> Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> ---
> drivers/clk/imx/clk-imx7ulp.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
> index ce30663..6668210 100644
> --- a/drivers/clk/imx/clk-imx7ulp.c
> +++ b/drivers/clk/imx/clk-imx7ulp.c
> @@ -151,7 +151,6 @@ static void __init imx7ulp_clk_pcc2_init(struct
> device_node *np)
> clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1",
> "nic1_clk", base + 0x20, 30);
> clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1",
> "nic1_bus_clk", base + 0x3c, 30);
> clks[IMX7ULP_CLK_DMA_MUX1] =
> imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
> - clks[IMX7ULP_CLK_SNVS] = imx_clk_hw_gate("snvs",
> "nic1_bus_clk", base + 0x8c, 30);
> clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam",
> "nic1_clk", base + 0x90, 30);
> clks[IMX7ULP_CLK_LPTPM4] = imx7ulp_clk_composite("lptpm4",
> periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base +
> 0x94);
> clks[IMX7ULP_CLK_LPTPM5] = imx7ulp_clk_composite("lptpm5",
> periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base +
> 0x98);
> --
> 2.7.4
