On Wed, 8 Aug 2007, Andi Kleen wrote:
> Not sure why the MSR varies between cores though.
Yeah that boggled me too.
> It's better to just make it a global instead.
Haven't gotten to figuring out how to do *that* yet... but here's a
cleanup for the detection function:
From: Cal Peake <[EMAIL PROTECTED]>
We only care about the lower 32-bits when reading the Interrupt Pending
Message Register so drop the 'hi' variable and use rdmsrl() instead.
Signed-off-by: Cal Peake <[EMAIL PROTECTED]>
--- ./arch/i386/kernel/cpu/amd.c~orig 2007-08-07 20:22:26.000000000 -0400
+++ ./arch/i386/kernel/cpu/amd.c 2007-08-07 20:23:22.000000000 -0400
@@ -34,7 +34,7 @@ __asm__(".align 4\nvide: ret");
/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
static __cpuinit int amd_apic_timer_broken(void)
{
- u32 lo, hi;
+ u32 msr;
u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
switch (eax & CPUID_XFAM) {
case CPUID_XFAM_K8:
@@ -42,8 +42,8 @@ static __cpuinit int amd_apic_timer_brok
break;
case CPUID_XFAM_10H:
case CPUID_XFAM_11H:
- rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
- if (lo & ENABLE_C1E_MASK)
+ rdmsrl(MSR_K8_ENABLE_C1E, msr);
+ if (msr & ENABLE_C1E_MASK)
return 1;
break;
default:
-
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