[PATCH 2/2] EDAC/mce_amd: Decode MCA_STATUS in bit definition order

[Ghannam, Yazen]

From: Yazen Ghannam <yazen.ghan...@amd.com>

Reorder how we decode the bits in MCA_STATUS to follow how their defined
in the register.

The order is as follows:

Bit : Decode
61  : UC
59  : MiscV
58  : AddrV
57  : PCC
55  : TCC
53  : SyndV
46  : CECC
45  : UECC
44  : Deferred
43  : Poison
40  : Scrub

Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
 drivers/edac/mce_amd.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index b349c22bb386..0a1814dad6cf 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -1051,26 +1051,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long 
val, void *data)
                ((m->status & MCI_STATUS_UC)    ? "UE"    :
                 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),
                ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
-               ((m->status & MCI_STATUS_PCC)   ? "PCC"   : "-"),
-               ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
-
-       if (fam >= 0x15) {
-               pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : 
"-"));
-
-               /* F15h, bank4, bit 43 is part of McaStatSubCache. */
-               if (fam != 0x15 || m->bank != 4)
-                       pr_cont("|%s", (m->status & MCI_STATUS_POISON ? 
"Poison" : "-"));
-       }
+               ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"),
+               ((m->status & MCI_STATUS_PCC)   ? "PCC"   : "-"));
 
        if (boot_cpu_has(X86_FEATURE_SMCA)) {
                u32 low, high;
                u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
 
-               pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : 
"-"));
-
                if (!rdmsr_safe(addr, &low, &high) &&
                    (low & MCI_CONFIG_MCAX))
                        pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : 
"-"));
+
+               pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : 
"-"));
        }
 
        /* do the two bits[14:13] together */
@@ -1078,6 +1070,14 @@ amd_decode_mce(struct notifier_block *nb, unsigned long 
val, void *data)
        if (ecc)
                pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
 
+       if (fam >= 0x15) {
+               pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : 
"-"));
+
+               /* F15h, bank4, bit 43 is part of McaStatSubCache. */
+               if (fam != 0x15 || m->bank != 4)
+                       pr_cont("|%s", (m->status & MCI_STATUS_POISON ? 
"Poison" : "-"));
+       }
+
        if (fam >= 0x17)
                pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));
 
-- 
2.17.1