Am Donnerstag, den 07.02.2019, 16:29 -0800 schrieb Andrey Smirnov:
> According to NXP's FAE feedback and a comment in ATF firmware, PCIE1
> and PCIE2 power domains can't really be used independently. Due to
> shared reset line both power domains have to be turned on at the same
> time. Account for that quirk by combining PCIE power domains into a
> single 'pgc_pcie' power domain.
> 
> Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
> Cc: Shawn Guo <shawn...@kernel.org>
> Cc: Fabio Estevam <fabio.este...@nxp.com>
> Cc: Chris Healy <cphe...@gmail.com>
> Cc: Lucas Stach <l.st...@pengutronix.de>
> Cc: Leonard Crestez <leonard.cres...@nxp.com>
> Cc: "A.s. Dong" <aisheng.d...@nxp.com>
> Cc: Richard Zhu <hongxing....@nxp.com>
> Cc: linux-...@nxp.com
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

Nit below, otherwise:

Reviewed-by: Lucas Stach <l.st...@pengutronix.de>

> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 50436bd393ed..89babc531380 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -273,9 +273,28 @@
>                                               reg = <IMX8M_POWER_DOMAIN_MIPI>;
>                                       };
>  
> -                                     pgc_pcie1: power-domain@1 {
> +                                     /*
> +                                      * As per comment in ATF source code:
> +                                      *
> +                                      * PCIE1 and PCIE2 share the
> +                                      * same reset signal, if we
> +                                      * power down PCIE2, PCIE1
> +                                      * will be held in reset too.
> +                                      *
> +                                      * So instead of creating two
> +                                      * separate power domains for
> +                                      * PCIE1 and PCIE2. We create
> +                                      * a link between 1 and 10 and

1 and 10 is not something that directly shows up in the DTS, so I think
it could be confusing to the reader. I would just state that as "link
between both" or something to that tune.

> +                                      * use what was supposed to be
> +                                      * domain 1 as a shared PCIE
> +                                      * power domain powering both
> +                                      * PCIE1 and PCIE2 at the same
> +                                      * time
> +                                      */
> +                                     pgc_pcie: power-domain@1 {
>                                               #power-domain-cells = <0>;
>                                               reg = 
> <IMX8M_POWER_DOMAIN_PCIE1>;
> +                                             power-domains = <&pgc_pcie2>;
>                                       };
>  
>                                       pgc_otg1: power-domain@2 {

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