From: Arnaldo Carvalho de Melo <a...@redhat.com>
To get the changes from:
a0aea130afeb ("KVM: x86: Add CPUID support for new instruction WBNOINVD")
20c3a2c33e9f ("x86/speculation: Add support for STIBP always-on preferred
mode")
Cc: Adrian Hunter <adrian.hun...@intel.com>
Cc: Jiri Olsa <jo...@kernel.org>
Cc: Namhyung Kim <namhy...@kernel.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Robert Hoo <robert...@linux.intel.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Thomas Lendacky <thomas.lenda...@amd.com>
Link: https://lkml.kernel.org/n/tip-aonti3bu9rhnqe5hlawbi...@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <a...@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h
b/tools/arch/x86/include/asm/cpufeatures.h
index 28c4a502b419..6d6122524711 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -281,9 +281,11 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired
Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP
error pointers */
+#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch
Prediction Barrier */
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch
Restricted Speculation */
#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect
Branch Predictors */
+#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread
Indirect Branch Predictors always-on preferred */
#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store
Bypass Disable */
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative
Store Bypass Disable */
#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store
Bypass is fixed in hardware. */
--
2.20.1
