On Fri, Nov 30, 2018 at 09:34:19AM +0000, Liu,Qi(ACU-T1) wrote:
> Is there a semantic divergence between x86 instruction "LOCK cmpxchg"
> and the macro cmpxchg defined in linux kernel? The former guarantee
> full barrier in any case, and the latter only imply barrier in case of
> success?
> So, we use
> smp_mb__before_atomic()
> cmpxchg_relaxed() // no barrier
> to get rid of the redundant barrier
> smp_mb__before_atomic()
> cmpxchg() // imply a redundant barrier when successing
No, it is all horribly more complicated :-)
On x86: cmpxchg_relaxed() == cmpxchg() == LOCK CMPXCHG, however
smp_mb__{before,after}_atomic() is a no-op.
On say arm OTOH: cmpxchg_relaxed() == LL/SC, but then
smp_mb__{before,after}_atomic() is smp_mb(), such that: cmpxchg() := {
smp_mb__before_atomic(); cmpxchg_relaxed(); smp_mb__after_atomic(); }
The difference is that on x86 atomic instructions unconditionally imply
memory ordering; whereas on ARM they do not.
