>>> On 21.11.18 at 14:49, <david.lai...@aculab.com> wrote: > From: Jan Beulich >> Sent: 21 November 2018 13:03 >> >> >>> On 21.11.18 at 12:55, <david.lai...@aculab.com> wrote: >> > From: Jan Beulich >> >> Sent: 21 November 2018 10:11 >> >> >> >> Add missing insn suffixes and use rmwcc.h just like was (more or less) >> >> recently done for bitops.h as well. >> > >> > Why? bts (etc) on memory don't really have an 'operand size'. >> >> Of course they do - depending on operand size they operate on >> 2-, 4-, or 8-byte quantities. When the second operand is a >> register, the suffix is redundant (but doesn't hurt), but when >> the second operand is an immediate, the assembler (in AT&T >> syntax) has no way of knowing what operand size you mean. > > You need to RTFM.
Excuse me? How about you look at this table from the SDM (format of course comes out better in the .pdf): 0F AB /r BTS r/m16, r16 MR Valid Valid Store selected bit in CF flag and set. 0F AB /r BTS r/m32, r32 MR Valid Valid Store selected bit in CF flag and set. REX.W + 0F AB /r BTS r/m64, r64 MR Valid N.E. Store selected bit in CF flag and set. 0F BA /5 ib BTS r/m16, imm8 MI Valid Valid Store selected bit in CF flag and set. 0F BA /5 ib BTS r/m32, imm8 MI Valid Valid Store selected bit in CF flag and set. REX.W + 0F BA /5 ib BTS r/m64, imm8 MI Valid N.E. Store selected bit in CF flag and set. Please read manuals yourself before making such statements. > Regardless of the 'operand size' the 'bit' instructions do a 32 bit aligned > 32 bit wide read/modify/write cycle. > > The 'operand size' does affect whether the bit number (which is signed) > comes from %cl (8 bits), %cx (16 bits), %rcx (32 bits) or (%ecx) 64 bits. > But that is implicit in the register name used. There is no form with %cl as operand. Instead there are forms with an immediate operand. Jan
