From: Christoph Lameter <[EMAIL PROTECTED]> Date: Mon, 9 Jul 2007 08:45:42 -0700 (PDT)
> On Sat, 7 Jul 2007, David Miller wrote: > > > From: Christoph Lameter <[EMAIL PROTECTED]> > > Date: Sat, 07 Jul 2007 20:49:52 -0700 > > > > > A cmpxchg is less costly than interrupt enabe/disable > > > > This is cpu dependant, and in fact not true at all on Niagara > > and several of the cpus in the UltraSPARC family. > > Hmmm... So have alternate aloc/free paths depending on the cpu? As Andi seemed to imply I don't even think cmpxchg is faster than interrupt enable/disable on current generation AMD x86_64 chips, so are you targetting this optimization solely at Intel x86 Core Duo 32-bit chips? That's the only one I can see which will benefit from this. Are you going to probe the cpu sub-type and patch SLUB? I really don't think this optimization is wise as even if you could decide at build time, it's going to be a maintainence and debugging nightmare to have to field bug reports given two different locking schemes. Please reconsider this change, thanks. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
