-----Original Message----- From: Li Yang <[email protected]> Sent: 2018年10月27日 4:29 To: Xiaowei Bao <[email protected]> Cc: Arnd Bergmann <[email protected]>; Rob Herring <[email protected]>; Bjorn Helgaas <[email protected]>; Mark Rutland <[email protected]>; Shawn Guo <[email protected]>; [email protected]; [email protected]; Greg Kroah-Hartman <[email protected]>; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; Kate Stewart <[email protected]>; [email protected]; Philippe Ombredanne <[email protected]>; [email protected]; [email protected]; [email protected]; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <[email protected]>; lkml <[email protected]>; moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <[email protected]>; linuxppc-dev <[email protected]> Subject: Re: [PATCH 3/6] PCI: layerscape: Add the EP mode support
On Fri, Oct 26, 2018 at 2:43 AM Xiaowei Bao <[email protected]> wrote: > > > > -----Original Message----- > From: [email protected] <[email protected]> On Behalf Of > Arnd Bergmann > Sent: 2018年10月26日 15:01 > To: Xiaowei Bao <[email protected]> > Cc: Rob Herring <[email protected]>; [email protected]; > [email protected]; [email protected]; Leo Li > <[email protected]>; [email protected]; [email protected]; > [email protected]; M.h. Lian <[email protected]>; Mingkai > Hu <[email protected]>; Roy Zang <[email protected]>; > [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; [email protected]; > [email protected]; [email protected] > Subject: Re: [PATCH 3/6] PCI: layerscape: Add the EP mode support > > On 10/26/18, Xiaowei Bao <[email protected]> wrote: > > From: Rob Herring <[email protected]> > >> On Thu, Oct 25, 2018 at 07:08:58PM +0800, Xiaowei Bao wrote: > >>> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" > >>> "fsl,ls2088a-pcie" > >>> "fsl,ls1088a-pcie" > >>> "fsl,ls1046a-pcie" > >>> "fsl,ls1012a-pcie > >>> + EP mode: > >>> + "fsl,ls-pcie-ep" > >> > > > You need SoC specific compatibles for the same reasons as the RC. > > > > [Xiaowei Bao] I want to contains all layerscape platform use one > > compatible if the PCIe controller work in EP mode. > > Do you mean only one of the SoCs that support RC mode has EP mode? > I think you still need a SoC specific compatible as Rob explained, in case > there will be a second one in the future. > > If you want to ensure that you don't have to update the device driver for > each new chip that comes in when the EP mode is compatible, the way this is > handled is to list multiple values in the compatible property, listing the > first SoC that introduced the specific version of that IP block as the most > generic type, e.g. > > copatible = "fsl,ls2088a-pcie-ep", "fsl,ls1012a-pcie-ep", > "snps,dw-pcie-ep"; > > For consistency, it probably is best to match each RC mode value with the > corresponding EP mode string for each device that can support both (if there > is more than one). > > Arnd > [Xiaowei Bao] My mean is that the ls-pcie-ep compatibles will contain all > layerscape SOCs of NXP, e.g: ls1046a-pcie-ep, fsl,ls2088a-pcie-ep, > ls2088a-pcie-ep and so on, other layerscape SOCs have not test except the > ls1046a, I think it is compatible if the new chip or other SOCs use the DW > core, OK, I will discuss this issue internally, and reply to you later. You can define a generic compatible string for the EP mode of all these platforms. But like Rob and Arnd mentioned, it is good to also define the SoC specific compatible strings just in case that we need special treatment for certain SoCs in the future. Regards, Leo [Xiaowei Bao] Hi Leo, OK, I will add the SoC specific compatible strings in patch-v2, thanks a lot.
