> Also cache misses in this situation tend to be much more than 48 cycles > (even an K8 with integrated memory controller with fastest DIMMs is > slower than that) Mathieu probably measured an L2 miss, not a load from > RAM. > Load from RAM can be hundreds of ns in the worst case. >
The 48 cycles sounds to me like a memory load in an unloaded system, but it is quite low. I wonder how it was measured... tong - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
