On Thu, Sep 06, 2018 at 10:33:39AM +0200, Jiri Kosina wrote:
> +/*
> + * The read-modify-write of the MSR doesn't need any race protection here,
> + * as we're running in atomic context.
> + */
> +static void enable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> + mask |= SPEC_CTRL_STIBP;
> + wrmsrl(MSR_IA32_SPEC_CTRL, mask);
> +}
> +
> +static void disable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> + mask &= ~SPEC_CTRL_STIBP;
> + wrmsrl(MSR_IA32_SPEC_CTRL, mask);
> +}
> +
> +void arch_smt_enable_errata(void)
> +{
> + if (stibp_needed()) {
> + pr_info("Spectre v2 cross-process SMT mitigation: Enabling
> STIBP\n");
> + on_each_cpu(enable_stibp, NULL, 1);
> + }
> +}
Shouldn't this add the STIBP bit to 'x86_spec_ctrl_base'? Otherwise
won't it get overwritten in places like vmexit,
firmware_restrict_branch_speculation_end(), intel_set_ssb_state(), etc?
--
Josh
