Andi Kleen <[EMAIL PROTECTED]> writes: >> For the K7 and K8 cores AMD systems are exactly like Intel systems >> with respect to MTRRs (although AMD systems also have additional registers) >> For the K9 core (i.e. AMD socket F or the K8 with DDR2 support) there > > It's called K8RevE, not K9
revF not revE. I think AMD was code-naming that K9 before the socket F part was released. revE was the last DDR rev of the K8 core. >> is an additional mechanism that makes everything above 4G write-back >> cacheable without using any MTRRs. > > ... but not BIOS use this mechanism (often there are BIOS switches > for several MTRR models or it is just the wrong one hardcoded), so Linux > should detect the broken cases. Yes. They are and I have seen at least two motherboards that fit this description. I almost freaked out looking at a system with 16G and only 4G setup to be cached. The painful bit is I have also seen such a system with not all of the lower 4G cached. Which caused some interesting booting issues. Eric - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
